We consider synchronous sequential circuits made from combinatorial components interleaved with banks of flip flops containing the state of the circuits
This circuit has two stable states for a given input - it is called bistable
In a latch a pulse on set or reset indicates what the new state should be, and when it should change
Designing circuits becomes easier if we can separate what and when
D - data input, Defines what the new value should be
CLK - clock input. Defines when the new value should arise
In the D-latch the output can change whenever the clock is high. Even better is we can make it change only at the moment the clock goes high
D flip-flop copies D to Q on the rising edge of the clock, and remembers its sate at all other times
Incorporates an additional input (enable) to control whether the data is loaded into the register or not
EN can control the input with a multiplexor, or can control the clock. This is called a gated clock.
Gated clocks can cause timing errors and glitches on the clock
How many transistors are needed to build the D flip-flop
Direct design can make more space efficient flip flops. Here 20 transistors
How would a latch and flip flow behave in the following setting?
The gates have a delay of 1ns
How does this circuit behave?
Suppose X=0, then Y=1 and Z=0, so X=1
This is an unstable or astable circuit
An improved D latch? Fewer gates, so fewer transistors!
Leads to race conditions - behaviour depends on which of the two routes through the circuits carries signal the fastest
Logically identical circuits may exhibit different behaviour depending on technicalities of the gate construction or at certain temperatures
The problems are caused by outputs being fed back into inputs: the circuits contain loops or cyclic paths
To avoid this we insert registers into cyclic paths:
If the clock is sufficiently slow, so that all inputs to the registers have settled before the next clock edge, then race conditions can’t arise
A synchronous sequential circuit consists of interconnected elements such that:
A synchronous sequential circuit has:
Which are synchronous sequential circuits?
The dynamic discipline restricts us to using circuits satisfying timing constraints that allow us to combine components
With these constraints we can think of signals as discrete in time as well as logic
Time between ticks (TC) must be at least tpcq+tpd+tsetup
Rearranging that we see that
tpcq+tsetup is called the sequencing overhead
The clock speed and sequencing overhead are normally fixed and the designer must work with them
Designers must get all elements of combinational logic to work within the bound on tpd in order for the circuit to be reliable
There is also a minimum delay requirement:
What is the max clock frequency?
Are there hold time violations?
Critical path goes through all 3 gates
$1/250ps$ = 4GHz
There would be a hold time violation
What is the max clock frequency now?
Are there hold time violations?
Suppose the input D to a flip flop is connected to a button
If D is unpressed or pressed when the clock rises, Q will be set to a stable state.
If F is in the process of being pressed when the clock rises, Q may be set to a metastable state.
The state will br driven to 1 or 0 eventually, but it may take time
A pair of flip-flops can be used to synchronise the input with the clock.
The value of D2 may be intermediate if D is not synchronised
If the resolution time of F1 is small enough compared to the clock rate, Q will be synchronised
Insert an additional register into the circuit
Insert another register in the circuit